Figure : A two stage opamp schematic
The project was done as part of the course work for "Non-classical device design" (EEE 6470) in the spring semester of 2008. The course was taught by Dr. Jerry Fossum. The aim of the project was to use finfets at 28 nano meter channel lengths and design analog circuits. I used the University of Florida Double Gate (UFDG) simulator developed by the SOI group at UF for simulating the circuit.
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Tags: Finfets, UFDG, spice, opamp, CMOS, two stage CMOS, double gates, 28 nano meter, 28nm, Compensation